Duration: 7h 55m | 34 Lessons | Video: 1280x720, 48kHz | 5.2 GB
Genre: eLearning | Language: English | Level: All levels
In this course you will learn to develop FPGAs with VHDL language, FPGA is an integrated circuit - a chip that is making complex calculations in parallel and can be program by the developer. today can be found in every smart phone, cars, plans, most of your electronics have FPGA.
Today, working as a FPGA developer is the most profitable job in Hardware development. And is a profession in great demand in every big company: apple, microsoft, intel, amazon, google and so many others!
If you want to work as a FPGA developer or just to know how to design an FPGA this is the course for you!
This Course was made for all levels by a professional electronic and computer engineer with a huge experience with FPGAs of all of the companies in the market. In this Course we will learn how to use Xilinx FPGAs tool - Vivado design suite. I will use VIVADO 2019.1 but the course is valid for any version of VIVADO including 2020.
In this course you will learn everything you need to know for using Vivado design suite. Vivado design suite is a tool that was crated by Xilinx and is used to design Xilinx FPGAs, simulating them and real-time debugging them and of course to program them.
This course was created for beginners who never used Vivado before, and also for students who wants more experience with the Vivado design suite, also this course can help even advanced users for knowing and understanding how to use and design more complex parts in this tool - like Pcie, Axi interface, Simulations with 3rd party tool(Modelsim,Questasim...), Zynq7000 processor and much more.
This course will help the Students understand everything they needs to know for working in big companies with Vivado design suite as a professional designers/engineers.
In this course the students will learn how to simulate their project with Vivado and also with 3rd party tool - Modelsim. Students with no experience at Modelsim will learn briefly about Modelsim but i can guarantee that after the Full Project part in the course you will control the Modelsim which is a really easy tool to learn.
At the end of the course it includes a Full Project of 2.5 hours, with PCIE communication and simulating the PCIE Cores. This way after you have learned all of the parts of how to start your own project, you can also go and build a big project by using all of the aspects learned on this course.
I am willing to add more full projects with different complicated IP's, so you will be able to use them as reference for your projects. my main goal is to make it easier for the students to be able to create any project they want.
The main topics this course will cover are:
How to download and install Vivado design suite 2019.1
How to download and install Modelsim
Create new project
Adding block design
Adding Xilinx IP cores
Xilinx Primitive Cores
Xilinx language templates
synthesize a project
Implementing the design
Creating Constraints
Generate Bitstream , Binstream and MCS files
Simulating the design through Vivado or Modelsim
Zynq 7000
Axi interfaces
Open SDK project
Real Time Integration with ILA - logic analyser
PCIE FULL Project with PCIE and Simulating the PCIE.
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