High-Level Synthesis for FPGA, Part 2 - Sequential Circuits
High-Level Synthesis for FPGA, Part 2 - Sequential Circuits
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + srt | Duration: 102 lectures (9h 28m) | Size: 7.02 GB
Logic Design with Vitis-HLS
What you'll learn:
Designing sequential logic circuits with C/C++ language using the HLS approach
Understanding the basic concepts of High-Level Synthesis (HLS)
Using HLS concepts for designing sequential logic circuits
HLS design flow for FPGAs
Working with Xilinx Vitis-HLS and Vivado design suite Toolsets
How to generate RTL hardware IPs using Vitis-HLS
Writing C-testbench in HLS
Implementing three exciting projects with HLS
Requirements
Understanding the basic concepts of C/C++ coding
"High-Level Synthesis for FPGA, Part 1 - Combinational Circuits" course
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado toolsets
Description
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).
It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.
This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.
This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.
Who this course is for
Hardware engineers
Software engineers who are interested in FPGA
Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
Digital Logic enthusiasts
Homepage
High-Level Synthesis for FPGA, Part 2 - Sequential Circuits
MP4 | Video: h264, 1280x720 | Audio: AAC, 44.1 KHz, 2 Ch
Genre: eLearning | Language: English + srt | Duration: 102 lectures (9h 28m) | Size: 7.02 GB
Logic Design with Vitis-HLS
What you'll learn:
Designing sequential logic circuits with C/C++ language using the HLS approach
Understanding the basic concepts of High-Level Synthesis (HLS)
Using HLS concepts for designing sequential logic circuits
HLS design flow for FPGAs
Working with Xilinx Vitis-HLS and Vivado design suite Toolsets
How to generate RTL hardware IPs using Vitis-HLS
Writing C-testbench in HLS
Implementing three exciting projects with HLS
Requirements
Understanding the basic concepts of C/C++ coding
"High-Level Synthesis for FPGA, Part 1 - Combinational Circuits" course
BASYS3 evaluation board
Xilinx Vitis-HLS and Vivado toolsets
Description
This course is an introduction to sequential circuits design in high-level synthesis (HLS). The goals of the course are describing, debugging and implementing sequential logic circuits on FPGAs using only C/C++ language without any help from HDLs (e.g., VHDL or Verilog).
It uses the Xilinx HLS software and hardware platforms to demonstrate real examples and applications. The course mainly uses the Xilinx Vitis-HLS toolset to describe, simulate and synthesise a high-level design description into the equivalent HDL code. The course also explains how to use the Integrated Logic Analyser (ILA) IP in Vivado to perform real-time debugging on the Basys3 board.
This course is the first of its kind that builds the HLS design flow and skills along with the digital logic circuit concepts from scratch. Along the course, you will follow several examples describing the HLS concepts and techniques. The course contains numerous quizzes and exercises for you to practice and master the proposed methods and approaches. In addition, the course utilises three exciting projects to put all the explained concepts together to design real circuits and hardware controllers.
This course is the second of a series of courses on HLS in designing hardware modules and accelerating algorithms on a target FPGA. Whereas this course focuses on sequential circuits, the first course explains how to describe combinational circuits in HLS. The other courses in the series will explain how to use HLS in designing advanced logic circuits, algorithm acceleration, and hybrid CPU+ FPGA heterogeneous systems.
Who this course is for
Hardware engineers
Software engineers who are interested in FPGA
Lecturers, researchers, professors who want to use FPGA-based HLS in lectures, courses or research
Digital Logic enthusiasts
Homepage
